1. Technical Field
The present invention relates to an electro-optical device, a driving circuit of the same, a driving method of the same, and an electronic apparatus capable of preventing the deterioration of display quality.
2. Related Art
In recent years, a reduced image is formed by a display panel using, for example, liquid crystal, and projectors for projecting the reduced image onto a screen or a wall surface by an optical system have become widespread. The projector does not have a function for forming an image as is and is supplied with image data (or image signals) from a host device, such as a personal computer or a television tuner. Since the image data designates the gray-scale level (brightness) of a pixel and is supplied in a vertical and horizontal scanning manner to the pixels arranged in a matrix, it is preferable that the panel used for the projector be driven in the above-mentioned manner. As a result, the panel used for the projector is generally of a point-sequential type in which the scanning lines are sequentially selected, the data lines are sequentially selected for a period of time when one scanning line row is selected (one horizontal scanning period) and data signals supplied to an image signal line are sampled to the selected data line. Here, the data signal is a signal obtained by properly converting the image data so as to be suitable for driving the liquid crystal.
In addition, in order to cope with a high-definition display image, a driving method called a phase expansion driving method has been considered. During one horizontal scanning period, the phase expansion driving method simultaneously selects a predetermined number of data lines belonging to each group, for example, six lines belonging to one block, and expands the image signal to be supplied to the pixel corresponding to the intersection of the selected scanning lines and the selected data lines by six times along the time axis to respectively sample them to the six data lines corresponding to the selected block.
In both the point-sequential method and the phase expansion method, the same manner is used for sampling the data signal to the data lines.
Here, the data lines are selected by the sampling signal (pulse). Specifically, sampling switches are provided between the image signal line and each data line, and the data signal is sampled to the data lines when the sampling switch is turned on according to the sampling signal. According to this structure, when the pulse widths of the sampling signals corresponding to adjacent data lines (block) overlap with each other, a different data signal from the original data signal is sampled, so that display quality is deteriorated.
Further, in recent years, there has been proposed a technique in which the pulse width of the sampling signal is made smaller by an enable pulse, and the sampling signals output before and after the phase in time do not overlap each other.
Since the panel has a structure in which transistors and various wiring lines are formed on a substrate made of, for example, glass, it is easy for a parasitic capacitor to generate a signal delay due to the wiring resistance. In particular, since a supply path of the enable pulse is different from that of the data signal, although the enable pulse is supplied to the panel so as to be synchronized with the data signal, in the panel, the phase of the enable pulse is deviated with respect to the data signal, so that it is not possible to generate suitable sampling signals.
In order to solve the above-mentioned problems, there has been disclosed a technology in which the monitoring signal supplied in synchronization with the enable pulse is supplied to the panel, the delayed or advanced deviation in the panel is detected, the phase of the enable pulse is adjusted according to the deviation, and the phase deviation of the enable pulse is changed.
In this technology, the phase adjustment is performed by inputting the master clock signal to the delay circuits connected in a cascaded manner, by selecting any one of the outputs of the delay circuits according to the delay time of the enable pulse, and by generating the enable pulse based on the selected master clock signal.
However, since the phase deviation of the enable pulse degrades the display quality, it is preferable that the precision of the phase adjustment be improved as much as possible. In this technology, since the minimum adjustment unit of the phase of the enable pulse depends on the delay time in each delay circuit, shortening the delay time in the delay circuit improves the adjustment precision. However, when the delay time in the delay circuit is short, the phase adjustment range of the enable pulse is narrowed, so that it is difficult to cope with the deviation of the enable pulse. On the other hand, in order to improve the phase adjustment precision of the enable pulse and to ensure the phase adjustment range, it is necessary that a plurality of delay circuits be connected to each other in a cascaded manner. As a result, there is a problem in that the structure becomes complicated.